1. The Field of the Invention
This invention relates to integrated semiconductor devices having isolation trenches, and to corresponding methods of manufacture.
2. Description of the Related Art
Background: Junction Isolated smart power technologies have the drawback of large lateral isolation structures, the area consumed by such structures being dependent on the required blocking voltage (the higher the voltage requirement, the more area needed). Vertical isolation is typically achieved by using highly doped implanted buried layers, requiring large thermal budgets.
Technologies processed on SOI use trench isolation, guaranteeing both lateral and vertical isolation through oxide layers. However, SOI is still expensive. Moreover, it has some inherent drawbacks for power switching and high voltage applications: (1) in order to reduce the effect of the back-gate effect (substrate potential), the buried oxide needs to be thick, (2) a thick oxide poses a barrier to the heat generated in a power switch due to the much lower thermal diffusivity in oxide compared to silicon. Hence, the devices will be much more prone to thermal destruction upon power switching, and have to be designed accordingly.
U.S. Pat. No. 4,140,558: B. T. Murphy et al., Isolation of Integrated Circuits Utilizing Selective Etching and Diffusion, Feb. 20, 1979 shows an early example of isolation.
U.S. Pat. No. 5,914,523: R. Bashir et al., “Semiconductor Device Trench Isolation Structure with Polysilicon Bias Contact”, Jun. 22, 1999 shows a trench isolation structure which includes a field oxide (FOX) layer on the surface of the semiconductor substrate and an isolation trench which extends vertically through the FOX layer and into the semiconductor substrate. Because of this structural arrangement of the isolation trench, the isolation trench has both semiconductor substrate sidewalls and FOX sidewalls.
U.S. Pat. No. 6,362,064: J. M. McGregor et al., “Elimination of Walk-Out in High Voltage Trench Isolated Devices”. Mar. 26, 2002 shows another example of trench isolation.
V. Parthasarathy et al., “A Multi-Trench Analog+Logic Protection (M-Trap) for Substrate Cross-talk Prevention in a 0.25 μm Smart Power Platform with 100V High-Side Capability”, ISPSD, pp 427-430 (2004) shows an example having multiple trenches.
FIG. 1 shows deep trench isolation as is currently used in the I3T50 technology of Amis (see F. De Pestel et al., “Development of a Robust 50V 0.35 μm Based Smart Power Technology Using Trench Isolation”, ISPSD 2003, pp 182-185.). On top of a p-substrate (103), a highly doped buried layer (102) of opposite doping (hence n-type) is created by ion implantation and subsequent thermal annealing. By using a blanket i.e. non-masked approach, a sheet resistance of ˜12-15 Ω/square can be achieved. A lower sheet resistance would require too high implantation doses, resulting in excessive defect formation. A low resistive buried layer is advantageous as it can serve as the drain terminal of quasi-vertical devices (hence low drain resistance), and because it also serves as the base of the (vertical) substrate PNP. A highly doped base yields an inefficient bipolar device, thus reducing the injection of carriers in the substrate. On top of the buried layer (102) a lowly doped epitaxial layer (101) of the same conductivity type as the buried layer is grown. All active devices will be made in the lowly doped epitaxial layer. In order to connect the buried layer (102) at the top silicon, a self-aligned sinker (104) of the same conductivity type as the buried layer (102) is made. Two epitaxial pockets are isolated from each other by a deep trench structure (110). After being etched, a thick isolation layer (106) is grown or deposited on the trench sidewall. This can be oxide, nitride, or a combination of both. The remaining trench is filled with a filling material (107) like polysilicon or oxide. Both epitaxial pockets are connected by metal contacts (108) and (109). If necessary, also the trench polyilicon (107) can be separately contacted and biased. In order to kill the parasitic MOS transistor (contact (108) serving e.g. as source, contact (109) serving as drain, filling layer (107) as gate electrode if conducting, insulator (106) as gate dielectric and (103) as substrate terminal), a p-stop implant (105) is implanted at the trench bottom after trench etch.
A similar structure is proposed in U.S. Pat. No. 4,140,558 (Feb. 20, 1979). However, the authors focus on [110] Si material with trenches along the <111> crystal orientations in order to be able to make narrow trenches. U.S. Pat. No. 5,943,578 and U.S. Pat. No. 667,226B2 also show similar structures.
FIG. 2 shows another known arrangement, as shown in U.S. Pat. No. 6,734,524. A deep trench is etched in a silicon layer stack comprising of a substrate (203) of a given conductivity type, a layer (204) of the same conductivity type but with a lower doping than (203), a layer (202) of the opposite conductivity type and finally a layer (201) of either conductivity type. The trench has an insulating layer (205) and is filled with a conductive material (206) for stress relief. The advantage of this structure is that it yields a good isolation from the substrate due to the low diffusion length of electrons (minority carriers) in the substrate.